Job Description

Send your resume to: : Click to see email-id MediaTek Banglore is Hiring for below positions:
DFT Engineer (3+ Years of Experience)
Responsibilities:
 SoC / Modem DFT for Smartphone
 ATPG Coverage analysis and improvements
 APTG/TFT pattern generation and optimization 
 Co-work with Smartphone SOC team to plan SoC/Modem DFT requirements
 Handle pre-silicon DFT verification and post-silicon DFT debug
 DFT clocking and DFT timing constraints 
 Doing scan synthesis and scan-chain analysis/stitching etc
 Doing DCT/DCG synthesis.
 Analyze DFT timings violations along with STA teams
 Work on the DFT methodologies for new technology nodes
Requirements:
 BE or MS/M.Tech degree in EE or related areas
 Minimum 2 years working experience on DFT and usage of tools like Tetramax
 Good experience in EDA tools like Synopsys Design Compiler, Primetime will be an added advantage 
 Understanding DFT requirements for lower technology nodes
 Ability to communicate effectively with multiple global cross-functional teams
 Enthusiastic and ability to be an independent player and also work in teams
STA Synthesis Engineer(3+ Years of Experience)
Responsibility:
 Synthesis and Timing closure on 28nm/16nm/10nm/Future sub-micron technologies at Block/SoC level
 Job Detail 
 Work on 28nm/16nm/10nm/Future sub-micron Technologies
 Co-work with RTL and DFT engineers, prepare SoC Top/Block level constraints
 Verify timing constraints with CCD
 Synthesis of Block and Top level and the Equivalence checks
 Develop floor-planning and CTS guidelines for layout
 Analyze pre-layout and post-layout timing, generate Timing and Power ECOs, work closely with layout engineers to achieve full chip timing closure
 Perform in-house quality check before P&R and after P&R.
 Power domain checks for Block and Top, CLP
Requirement :
 BS or M.Tech degree in EE or related
 1-6 years working experience with top/block level Synthesis, Timing closure (STA)
 Good Experience in DCT/DCG based Synthesis, Equivalence checks
 Good experience using PrimeTime and CCD
 Good understanding of Deep Sub Micron topics 
 Well versed with tcl / Perl script
 Experience handling UPF and Conformal Low Power checks
 Ability to communicate effectively with multiple global cross-functional teams
 Enthusiastic and ability to be an independent player and also work in teams 
 SoC level experience is a plus.
L2 / L3 Protocol development (2+ Years of Experience)
 Responsible for development, maintenance and support of cellular protocol stack software for mobile phones. 
 Proven software development experience in protocol layers 2/3 – RRC/RLC/MAC/PDCP, of at least one wireless telecoms standard namely 2/3/4G 
 Good understanding of 3GPP specifications. 
 Experience in embedded software development. 
 Good analytical and debugging skills. 
 Design/Development of stack on RTOS based platforms. 
 C and/or C++ programming experience.
Physical Design Engineer (3+ Years of Experience)
 Experienced Physical Design engineers to oversee the P&R process of core IPs and complex subsystems. 
 Engineer will be responsible for owning tapeouts of Blocks/Chips and integrates implementation environment components utilizing advanced flows and latest P&R tools. 
 Implementing complex IP/ASIC. 
 Responsible for Netlist to GDS physical design implementation of complex chips/blocks. 
 Responsible of signoff tasks, including power integrity, signal integrity, RC correlation and layout signoff flow in physical design team. Refer Now Send your resume to: : Click to see email-id