Job ID: R24548/ R25917/ R25366 / R22926 Location : Bangalore/Pune Experience level: 5+ yrs Education: BE/ B Tech/ ME/ M Tech / MS • B.Tech/BE/ME/Mtech with hands-on experience in physical design and verification. • Exp with ASIC design flow, hierarchical physical design strategies, methodologies and understand deep sub-micron technology issues. • Solid knowledge on LP Design, DFT, static timing analysis, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM. • Successful track records of taping out complex IP’s & SoC’s at 16/10/7/5 nm • Power user of Cadence implementation tools, such as Genus, Innovus, Quantus,Tempus, PVS, Voltus. • Automation and programming-minded, coding experience in Makefile/Tcl/Tk/Perl. • Self-motivated, able to work independently or as a team player, excellent verbal and written communication skills.