Job Description

Excellent Opportunity for VLSI Trained Freshers to work with Design IP R&D Team at Cadence, Noida.

Position: IP Design Verification Intern
Experience: 0 Years (Freshers from 2023 batch only with No prior work experience)
Qualification: B.Tech/M.Tech (EE/EC/CS) with CGPA > 7/10
Mandatory Skills: Apply only if you have strong understanding of Verilog and SV/UVM.
Additional skills: Good understanding of Digital Design concepts, C++/OOPS, Python scripting will help.
Salary: 4.8 - 5.4 LPA

Send your resume to:
: Click to see email-id
with following subject line:
"Internship Noida | Degree: B.Tech. Branch: EC | Year of Passing: 2023"