Job Description

Job Description: Driving/Owning Netlist to GDS convergence of leading edge processor graphics cores. This will include logic synthesis, physical synthesis, floor planning, formal verification, clock tree synthesis, static timing analysis, and IR drop analysis and layout verification. The job provides challenging opportunities to work on leading edge process technologies and design methodologies. Qualification: You should possess a Bachelor or Masters of Engineering degree in Electrical/ Electronic Engineering/ VLSI Engineering, with strong digital design basics. Familiarity in back-end design, expertise in synthesis to GDSII flows and skills in Register Transfer Level (RTL) analysis are an advantage; familiarity with tcl and Perl would be an added advantage. The candidate is expected to be enthusiastic in problem solving and should be able to resolve issues independently.