Job Description

Job Id        E1954722
Job Title        Memory Layout Design Engineer
Company - Division        Qualcomm Technologies, Inc. - CDMA Technology 
Job Area        Engineering - Hardware 
Location        India - Bangalore 
Job Overview        Qualcomm CDMA Technologies, a.k.a. QCT - http://www.qualcomm.com/qct/, is the world leader in wireless ICs powering the majority of 3G & 4G devices, is the largest fabless semiconductor in the world, and is consistently ranked near the top of Fortunes list of 100 Best Companies to Work For. QCT is actively seeking experienced Memory layout design engineers for Bangalore Design Centre. The memory layout team is responsible for developing custom as well as compiler memory designs from leafcell development to macro top level integration and physical verifications.
Minimum Qualifications        Understanding architecture and circuit design of various memory blocks.
- Area & parasitic optimized Leafcell layout development with good quality.
- Establish good communication with circuit designers and setup regular meetings to review critical path layout design and discussions on schedules & deliveries .
- Train and ramp up contractors who will be part of layout design team.
- Document critical designs and lessons learnt
Preferred Qualifications        Good understanding of memory functionality and electrical engineering concepts. - 2 to 8 years of experience in memory layout design. - Good understanding of deep submicron CMOS processes like 16/14/10 nm FinFET technologies. - Prefer experience in coding for automation SKILL/PERL. - Good knowledge in compiler integration. - Good exposure to usage of Cadence Virtuoso/VXL layout design and Mentor Graphics Calibre physical verification flow. - Good debugging skills to fix DRC, LVS, ERC. Macro power improvement using Totem IR analysis. - Work in a dynamic, team oriented environment and able to multi-task.
Education Requirements        B.Tech / M.Tech
*LI-IND